Wafer Charging Monitors, Inc.|
Wafer Charging Monitors, Inc. |
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ABSTRACT:Wafer charging damage during IC processing is the result of complex interactions between the wafer environment and the wafer. Understanding these interactions, and recognizing the relative importance of the different mechanisms capable of causing damage, are essential for successful diagnosis and control of charging damage during wafer manufacturing. This paper presents a unified perspective of charging damage in IC manufacturing, and from it derives a set of guidelines which can be used by equipment and IC manufacturers to avoid charging damage to ICs during wafer processing.
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(366 KB) | How to Avoid Charging Damage . . . |
ABSTRACT: Wafer charging damage in IC process equipment is the result of complex interactions between the wafer environment and the wafer. EEPROM-based sensors have been used recently to quantify the UV and charging characteristics of process tools and to examine the interactions between the wafer environment and the wafer. This paper discusses these topics, relates them to charging damage, and illustrates them with examples from experiments performed in different process tools.
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(466 KB) | Use of EEPROM-based Sensors . . . |
ABSTRACT: Wafer potentials and charging currents have been found to depend on the area of antennas connected to substrate. In a medium-density plasma dielectric etch tool, smaller substrate-connected antennas resulted in large charging potentials and current densities on separate test structures, whereas larger antennas produced much lower potentials and current densities. In a high-density plasma metal etch tool, this dependence was significantly smaller. These findings imply that circuit layout can strongly modulate damage in test structures and product.
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(144 KB) | The effect of Substrate Connections . . . |
ABSTRACT: Wafer charging damage in IC process equipment is the result of complex interactions between the wafer environment and the wafer. Quantifying the UV and charging characteristics of process tools, understanding the interactions between the wafer environment and the wafer, and recognizing the relative importance of the different mechanisms capable of causing damage are all important for successful diagnosis and control of charging damage during wafer manufacturing. This paper discusses these topics, and illustrates them with examples from experiments conducted in different process tools.
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(387 KB) | Wafer Charging in IC Process Equipment |
ABSTRACT: Results are presented which show that scribe lane structures can exert a significant influence on surface-substrate potentials and J-V characteristics measured on a wafer surface in plasma and ion-implant processes. The implications of this phenomenon for comparison of charging damage results obtained with charging test vehicles and product wafers are also discussed.
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(72 KB) | Influence of Scribe Lane Structures . . . |
CONCLUSIONS: We used a synchrotron radiation source to study the effect of VUV radiation on surface currents in dielectrics. We observed the effects of photon energy, electric field and interdigit spacing on VUV induced surface currents. We observed that the surface currents peak at photon energies of around 15 eV, increase linearly with electric field parallel to the surface and increase with decreasing interdigit spacing. These measured VUV induced surface currents are significant enough to change the charging seen during plasma processing.
ABSTRACT: The reasons underlying correlations and lack of correlations between SPIDER-MEM and CHARM-2 results are investigated for wafers implanted in a high-current, low energy ion implanter equipped with a plasma charge-control system. The results can be explained by taking into account the device structure and physics of the SPIDER-MEM devices, and the charging characteristics of the implanter. The work has important implications for comparison of results obtained from charging monitors and damage monitors.
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(43 KB) | Device Effects and Charging Damage . . . |
ABSTRACT: Charging effects were investigated in an Electron Cyclotron Resonance (ECR) Plasma-Enhanced CVD system using a variety of techniques including CHARM®-2 wafers [1,2], SPORT wafers [3] and full device antenna structures. In this work we show two factors affecting potential at the surface of the wafer which can be correlated to conditions where severe plasma damage is expected to occur. The CHARM-2 wafer data detected both the time-averaged (DC) and time-varying (AC) potentials. The DC component is shown to be a function of the applied wafer bias power while the AC component appears to be related to a low frequency potential fluctuation (a possible instability in the microwave generated magnetized plasma). Both of these signals can be reduced by increasing the processing pressure. Processes with higher pressure result in improved device damage immunity.
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(136 KB) | Effects of Processing Pressure . . . |
ABSTRACT: Wafer charging damage is a continuing problem in IC manufacturing. Inherent trade-offs limit simple solutions. Inadequate theoretical models and nonoptimized measurement techniques create difficulties in understanding. Recent work on charging with patterned resist suggests that major effects are unaccounted for in present models. Significant opportunities for reduction of wafer charging should become available when the influence of resist layout and placement is better understood.
ABSTRACT: A comparison of charging results obtained with Quantox® and CHARM®-2 is presented for the case of Arsenic implants at 80 KeV and 20 KeV, performed at doses of 5e14/cm2 and 5e15/cm2 at beam currents of 9 mA and 18 mA. The surface potential maps obtained by the Quantox are compared to the potentials and currents measured on the CHARM sensors, with the plasma charge control system on and off. The sensitivity of the Quantox system is compared for changes in the oxide thickness, the dose, and the beam density.
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(210 KB) | Comparison of Implant Charging Results . . . |
ABSTRACT: The mechanism responsible for charging damage to integrated circuit device insulators is treated as a plasma phenomenon, in which the beam/plasma drives potential differences on the process surface. J-V data obtained with the CHARM-2 diagnostic in a high current implanter (flood OFF) are fit with a plasma probe model. The fit indicates plasma buildup over the wafer surface. A cold plasma flood is suggested as a means of limiting potential differences during ion implantation.
ABSTRACT: The basic operation of charge monitors implemented at National Semiconductor are described. Called CHARM-2 (CHARge Monitor-second generation), the monitors are an effective tool for characterizing the in-situ wafer charging environment in IC process equipment. Ion implantation and plasma ashing examples compare the new monitors with conventional techniques.
ABSTRACT: Charging characteristics of As+, BF2+, and B+ high-current ion implants, performed at different energies and different plasma flood system settings, were measured using bare and resist-covered CHARMŽ-2 wafers patterned with a six-field mask containing holes ranging from 2 um to 0.5 um (clear and resist-covered fields were also used). The results show significant differences in the charging characteristics of high-current ion implanters compared to contemporary plasma-based process tools. The differences appear to be independent of ion energy, but depend on the set-up conditions of the plasma flood system used to limit positive charging caused by the ion beam. In contrast to plasma tools, the implants typically exhibited positive and negative potentials independent of hole size. The positive and negative current densities measured in the resist holes were also independent of hole size (and significantly higher than in the clear field). However, a 500 eV B+ implant with modern plasma flood control produced positive and negative potentials that scaled with hole size, as expected for electron shading, but with current densities below CHARMŽ-2 detection levels. This establishes an existence proof that optimal plasma flood can achieve near perfect current balance between the positive charging from the ion beam and the negative charging from the flood plasma. Altogether, these results suggest that charging damage in high-current ion implanters should be controllable when implant mask and device features are scaled down.
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(301 KB) | Investigation of Electron-Shading Effects . . . |
ABSTRACT: Charging characteristics of As+ and BF2+ high-current ion implants were measured using bare and resist-covered CHARM-2 wafers patterned with a six-field mask containing holes ranging from 2 um to 0.5 um (as well as clear and resist-covered fields). The results show surprising differences in the charging characteristics of high-current ion implanters compared to contemporary plasma-based process tools. In plasma tools, the "electron-shading" effects increase positive (and decrease negative) potentials and current densities as hole size decreases. On the contrary, high-current ion implants exhibited positive and negative potentials independent of hole size. The positive and negative current densities were also independent of hole size (but significantly higher than in the clear field). These results indicate that charging damage in high-current ion implanters should not increase when implant mask features are scaled down (other factors being equal). We also explain the apparent absence of damage in comtemporary high-current ion implanters in spite of the very high positive current densities and high positive potentials.
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(451 KB) | Control of Wafer Charging . . . |
ABSTRACT: Charge Control during ion implantation depends on the interaction of the ion beam plasma with the device wafer and other local sources of charged species. The key role of the net ion density, plasma electron temperature and plasma ion mass are discussed. The value of local monitoring of the current-voltage characteristics of the net plasma at the wafer surface with EEPROM sense and measurement devices is illustrated with effects of various charge control systems and the influence of resist patterning on the net current flow to the wafer. The special challenges of space charge control for sub-keV ion beams and the impact on local doping uniformity are also discussed.
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(64 KB) | Control of Wafer Charging . . . |
ABSTRACT: The accumulation of surface charges on electrically insulating layers during ion implantation affects the yield of charge-sensitive devices. Experiments with a typical secondary electron flood system and refinements to it demonstrate that improvements can be made over some common secondary electron flood systems currently in use. A redesigned SEF system has been proven to be an effective option for decreasing the high-energy secondary electrons that reach the wafer surface. Using consistent PM procedures, the 200 E SEF has been demonstrated to achieve a wide operating window for charge control. Real-time charge control can be achieved by use of the disk current monitor, with shower performance verification by scheduled CHARM-2 monitors.
ABSTRACT: Avoiding gate oxide damage due to excessive wafer charging has always been an issue with high current implanters. On the other hand, whether it is caused by shrinking of device dimensions, or its use as a backup for high current applications, charging level awareness becomes the primary limiting factor for running higher beam currents in medium current implanters. Often times, a cautious approach results in lower machine throughput. To the present, flooding the wafer with low energy electrons from electron showers (E-Shower) has been the widely accepted means of reducing wafer charging. The effectiveness of the E-shower in reducing charging as a function of primary ion current has been investigated in Eaton's medium current ion implanter. Extensive testing included over 180 bare and photo resist coated CHARM-2 charge monitors. Optimum shower settings will be presented and discussed in the light of CHARM-2 results and product split lot yields.
ABSTRACT: Gate to substrate charging during high current ion implantation correlates to gate oxide damage seen at product testing or during reliability assessment, as can be discovered by tedious statistical evaluations. However, variations in charging over time do not lend themselves to the same statistical analysis. Using CHARM-2 to proactively monitor charging on a consistent basis over 12 months detected adverse trends before charging levels impacted yield or reliability. Variations in charging levels also correlated to preventive maintenance schedules, indicating a need to implement optimum timing and procedures. Trends for different implanters demonstrate the results of successfully implementing procedural changes, which reduced peak charging potentials and minimized equipment drift.
ABSTRACT: Wafer charging effects in an Applied Materials 9500 implanter were studied for As implants with EEPROM-based sense and measurement devices and capacitors with either large oxide areas or large oxide-poly area ratios. The operation of the Plasma Flood Source; arc discharge current, guide tube voltage and confinement magnets, were varied to study the effects on these various charge monitors. The large-area oxide capacitors responded to conditions that increased the negative charge flows to the wafers. The large-area antenna structures responded to conditions that produced positive current flows.
ABSTRACT: A unified view of wafer charging effects during ion implantation has been developed based on (1) measurements of plasma current-voltage (J-V) characteristics with wafer-based, EEPROM sensors and (2) a viable model which describes the main features of the J-V characteristics of the ion beam plasma at the wafer surface. The beam-plasma model includes contributions from the energetic ion beam, background slow ions created by collisions, ions created by arc discharges and thermal electrons. The model describes the positive and negative charging behavior of "raw" ion beams (with no charge control systems) and ion beams combined with charge control sources of electrons, dilute plasmas or dense plasma floods.
ABSTRACT: This paper describes the use of CHARM-2 charge monitor wafers as a BIR (building in reliability) tool to identify, monitor and ultimately reduce implanter charging levels, resulting in increased die yields and enhanced product and equipment reliability. An Ion Implant engineering group at National Semiconductor Corporation has actively used CHARM-2 wafers to quantify charge potential levels existing in high current ion implanters, to baseline and monitor their set of four high current implanters, and to correlate die-level charging patterns on CHARM-2 wafers to product wafer yield patterns. CHARM-2 wafers have been successfully used to determine the effects of implanter equipment modifications and process changes on wafer charging. These equipment modifications have resulted in reduced wafer charging levels and have, therefore, helped to resolve charging-related product yield and reliability issues. The equipment and process modifications implemented with the aid of CHARM-2 wafers have also resulted in significantly improved equipment reliability and increased process robustness. Because of the consistently high degree of correlation of CHARM-2 charging patterns to product wafer yields patterns, CHARM-2 wafers serve as an effective in-line implant charge monitor in a manufacturing environment.
SUMMARY: Plasma process induced gate oxide damage was found in early process development stages. Device data showed unacceptable burn-in failure. By utilizing multiple test vehicles, the underlying cause of oxide damage was identified. This study showed that no single methodology is adequate for controlling the damage. A combination of the monitoring techniques is required to understand root cause of damage and how to optimize the process or equipment. The plasma process was optimized and verified with CHARM-2 monitor response. Further device data verification indicated no gate oxide damage was found with new improved process. The fast turnaround time of plasma monitors were essential to understand and determine the plasma damage source. Understanding the relationship between plasma monitor response and plasma process is a key point to identify the source of the damage. A fingerprint of plasma process is very useful for process control and defect reduction.
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(184 KB) | Comparison of CHARM-2 and Surface Potential Measurement . . . |
SUMMARY: In summary the question of whether or not thinner gate oxide is less susceptible to plasma-charging damage depends on a number of factors. One important factor is the definition of damage itself. The measurement method is linked to the definition of damage. When the charging current is low and charging voltage is high, thinner oxides are indeed far less prone to damage. When the charging current is high and charging voltage is low, like in most new plasma systems, thinner oxides are more susceptible to damage. In a very crude way, one may conclude that older plasma systems tend to belong to the low current, high charging voltage class while modern plasma equipment tends to belong to the high current, low charging voltage class. In this sense, it is the concomitant change to high density plasma processing with advanced technology where thinner gate oxides are used that make plasma charging damage continue to be a major problem.
SUMMARY: To summarize, the SPM method produces a voltage map that does not always correlate with damage. Since a highly non-uniform or high value SPM map does not imply damage, nor does a uniform and low value map imply no damage, it cannot be used as a damage monitor directly. Until one understands how and where the residual charges are created, the relation between SPM and plasma damage cannot be established. Although we provided a possible explanation for the residual charge distribution for our specific case, it cannot be generalized to all situations.
ABSTRACT: Although electron shading is currently the dominant damage mechanism in high density etchers, other types of damage that are plasma uniformity or RF related can occur. Case studies are presented that illustrate the utility of CHARM in detecting charge damage in these non-conventional cases. The utility of CHARM will also be shown in its ability to assist with hardware development.
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(531 KB) | Utility of CHARM-2 in Diagnosing . . . |
ABSTRACT: Resist stripping and cleaning is evaluated on a RF asher. A combination of RF and MW power can be used to enhance the stripping efficiency in the asher. The RIE components of a plasma are capable of producing plasma damage (can be observed in structures such as thin gate oxide underneath poly lines). In this evaluation, both metal antenna structures and Charm-2 wafers were used to monitor plasma charging. No plasma charging was observed using the standard O2/N2H2 plasma, but high plasma charge voltages could be observed with NF3 addition. The plasma characteristics were studied using optical emission spectroscopy. Analysis of the results suggests that plasma charging can be induced by a combination of RF and free fluorine species in the plasma.
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(204 KB) | Impact of F Species on Plasma Charge Damage . . . |
ABSTRACT: Plasma damage mechanisms can be very complex, especially when manufacturing non-volatile memories such as EPROM and flash memories. Plasma damage at via etch can manifest itself as a charge retention failure in the memory cell during product testing. This paper investigates the interaction of UV radiation, classical plasma charging due to non-uniform plasma, and standard integrated circuit fabrication procedures in order to propose an apparent charge loss failure mechanism for non-volatile memories.
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(141 KB) | Mechanism of Charge Induced Plasma Damage . . . |
ABSTRACT: Potentials and current densities imposed on device structures during oxide etching due to electron shading effects are presented. Comparison of results obtained in etchers exhibiting good plasma uniformity with results from etchers exhibiting plasma non-uniformity emphasizes the importance of uniform plasma to minimize charging damage during IC manufacturing.
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(215 KB) | Electron-Shading Effects During Oxide Etching . . . |
ABSTRACT: A bare CHARM-2 wafer has been evaluated in a Magnetically Enhanced Reactive Ion Etching (MERIE) apparatus in order to investigate the effect of a magnetic field on the charging phenomena. The monitor device responded, showing some correlation to the magnetic field. On investigation of the mechanism of the response, it appeared the response on the wafer consisted of two factors. One mechanism was demonstrated to be wafer chucking and de-chucking. The other mechanism explored was the MERIE RF plasma itself. It was shown that by optimization of the wafer chucking / de-chucking sequence and RF plasma condition, the response was greatly reduced. Also by utilizing this technique it was demonstrated that a CHARM-2 wafer could be processed without any appreciable fingerprints from the magnetic field. The optimized recipe and sequence were also applied to Tokyo Electron Limited (TEL) internal antenna MOS device which allow the estimation of electron shading effects in order to investigate the correlation between the two types of devices.
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(398 KB) | Influence of Etch Process Sequence . . . |
ABSTRACT: In this work, a CHARM-2 wafer with high aspect ratio resist patterns has been used to quantitatively characterize the electron-shading effect in a HDP oxide etch reactor. Moreover, we show by the decrease of the maximum collected current that an ion shading phenomenon also occurs for the highest aspect ratio. Finally, a careful analysis of antenna ratio effects may indicate the importance of UV assisted leakage current.
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(92 KB) | Electron-Shading Characterization . . . |
ABSTRACT: Via charging currents during via over-etch have been measured for the first time using CHARM-2 wafers and a special-purpose CHARM-2 compatible photoresist mask with varying via density. The measurements confirm previous findings which showed increased charging potentials and current densities in the presence of patterned resist. The measurements also show the presence of an additional effect - an increase in via charging currents with decreasing via density. This effect may have considerable implications for product damage, and for the evaluation and analysis of resist aspect-ratio dependent charging damage.
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(86 KB) | Quantifying Via Charging Currents . . . |
ABSTRACT: It is becoming increasingly evident that pattern dependent charging or electron shading is a significant charging mechanism for high density plasma etch systems. This mechanism, described by Hashimoto, can occur in uniform plasmas and is caused by the difference in isotropy of electrons and ions crossing the plasma sheath to the wafer surface. As electrons and ions interact differently with closely spaced structures on the surface of the wafer this leads to a differential charging of the structure with the top charging more negatively than the bottom. In this paper the voltages and currents developed by electron shading at the wafer surface are measured directly using a modified CHARM wafer.
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(118 KB) | Study of Pattern Dependent Charging . . . |
ABSTRACT: A CHARM-2 investigation of wafer charging during ECR etching revealed regions of highly localized negative charging, with current densities approaching -3 mA/cm2 at -10V. The highly localized regions of negative charging emphasize the need for ECR etcher characterization using charging monitors having high spatial resolution, and means for verifying the certainty of results.
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(163 KB) | Characterization of Wafer Charging in ECR Etching . . . |
ABSTRACT: A CHARM-2 investigation of wafer charging during via etching shows that wafer surface conditions strongly influence the observed results. Under identical process conditions, bare wafers underestimate the charging results. When wafers are covered with patterned resist, much higher surface-substrate potentials and current densities are observed.
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(111 KB) | Quantifying Wafer Charging During Via Etch |
ABSTRACT: Although the effects of photoresist on wafer charging during high current ion implantation have been previously reported [1-4], the resist layouts did not always simulate resist placement on product wafers, making it difficult to determine how relevant the results were to charging experienced by product wafers. Building on previous work, this presentation describes a general approach to resist mask design, intended to emulate resist placement on product wafers. This approach is applied to the design of four-field reticles for use with the CHARM-2 monitors to provide a tool for optimization of implant conditions to minimize resist-mediated empirically-based modeling of resist-mediated charging phenomena. Both dark-field and light-field designs are described. The masks described here were used in a comprehensive study of resist-mediated wafer charging on the Applied Materials 9500xR [5].
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(96 KB) | Photoresist Mask Design . . . |
ABSTRACT: The effects of ion energy, accumulated dose, photoresist coverage and patterning were studied for As+ implants at 40, 60 and 120 keV and total doses from 1x1014 to 1016 As/cm2. The effect of photoresist coverage, ion energy and dose on positive and negative potentials and j-V characteristics are presented. J-V data are fit with a beam plasma model that describes both positive and negative charging with a consistent set of plasma parameters.
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(134 KB) | Photoresist Effects on Wafer Charging Control . . . |
ABSTRACT: Surface-substrate potentials and charge fluxes observed during a high-current Arsenic implant on wafer half-covered with photoresist were quantified using a CHARM-2 charging monitor wafer. High negative potentials were observed on the bare portion of the wafer, while positive potentials were observed on the photoresist covered portion of the wafer. Substantially enhanced positive charge-flux was observed near the resist edge, on the bare side of the wafer. A model is proposed to explains these phenonema.
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(123 KB) | Influence of Photoresist . . . During High Current Arsenic Implant . . . |
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